The present invention relates to program modification, and more specifically, to program modification used in a computer system which executes programs fixed on instruction ROM and the like.
(General Background)
Conventional program modification devices include devices with a register for modification and devices containing indirect jump instructions in programs.
One such program modification device will be described as follows with reference to the drawings. (This device should be more strictly referred to as a program device provided with a function of modifying and executing programs fixed on ROM or the like; however, it is simply referred to as the program modification device).
FIG. 1 shows the entire structure of this conventional program modification device, and FIG. 2 shows the details of its main part.
In FIG. 1 the program modification device comprises a CPU core unit 1 including an execution unit 2 and an instruction acquisition unit 3, an instruction ROM 4 which stores programs, a program monitor unit 5 which checks whether the program portion which is going to be executed is a program portion (program data) to be modified or not, and an acquired instruction switch unit 6 which switches between acquiring the instruction the instruction acquisition unit 3 is going to execute from the instruction ROM 4 or acquiring it from a modification target program storage memory A, which will be described later, based on the determination of the program monitor unit 4.
The program modification device further comprises modifying address registers 7 which store the addresses of program data that need to be modified (hereinafter referred to as the modification source program data) and the addresses of program data that are modified and executed instead of the modification source program data (hereinafter referred to as the modification target program data) in pairs; a modification target program storage memory A 8 which stores modification target program data; an indirect call instruction row 9 contained in the instruction ROM 4; an indirect call table 10 which is referred to by the indirect call instruction row 9; and a modification target program storage memory B 11 which stores branch target program data branching in the indirect call table 10 (when there is no modification in a program, the branch target in the indirect call table 10 is in the ROM 4).
It goes without saying that this program modification device may further comprise a CRT or a liquid crystal display device, a keyboard, clock signal generation means, CD-ROM readout means, and a code correction unit, depending on the use of the computer system equipped with the program modification device.
In terms of the object of the present invention, the modification target program storage memory A 8 and the modifying address registers 7 are dispensable unless the programs in the instruction ROM 4 or the CD-ROM but also a so-called address group consisting of consecutive addresses, a specific region on memory, and a specific one memory among plural memories.
The following is a continuation of the description of the conventional program modification device.
FIG. 2 (1) is a conceptual illustration showing the inside of the instruction ROM 4. FIG. 2 (2) is a conceptual illustration showing the inside of the modifying address registers 7. FIG. 2 (3) is a conceptual illustration showing the inside of the modification target program storage memory A 8. FIG. 2 (4) is a conceptual illustration showing the inside of the indirect call table 10. FIG. 2 (5) is a conceptual illustration of the modification target program storage memory B 11.
The behavior of the program modification device will be described as follows.
Assume that addresses A1 and A2 in the instruction ROM 4 shown in FIG. 2 (1) are the addresses of the modification source program data with errors, and the program data at addresses B1 and B2 shown in FIG. 2 (2) are executed instead of the program data at these addresses A1 and A2, respectively.
Also assume that the indirect call instruction row in the instruction ROM 4 shown in FIG. 2 (1), which branches to the address a1 in the instruction ROM 4, is so modified as to branch to the address b1 in the modification target program memory B 11 as shown in FIG. 2 (4).
1) In order to execute the program data of the addresses B1 and B2 instead of the program data of the addresses A1 and A2, the addresses A1 and B1 as a pair and the addresses A2 and B2 as another pair are written into the modifying address registers 7 as shown in FIG. 2 (2). Furthermore, the indirect call table 10 shown in FIG. 2 (4) is changed from the address a1 which is before the modification to the address b1 which is after the modification.
2) The instruction acquisition unit 3 sequentially acquires instructions from the instruction ROM 4, and the execution unit 2 executes the instructions.
3) The program monitor unit 5 continuously checks whether or not the address of program data acquired by the instruction acquisition unit 3 agrees with the address of the modification source program data in the modifying address registers 7 by referring to the modifying address registers 7.
4) When the instruction acquisition unit 3 tries to acquire program data from the address A1 in the instruction ROM 4, the program monitor unit 5 detects agreement between the address 1 and the address of the modification source program data which is written in the modifying address registers 7. Then, the program monitor unit 5 makes the acquired instruction switch unit 6 acquire not the program data at the address A1 but the program data at the address B1, which is stored with the address A1 in a pair.
5) The acquired instruction switch unit 6 switches the instruction acquisition unit 3 so that the unit 3 acquires instructions not from the address A1 in the instruction ROM 4 but from the address B1 on the modification target program storage memory A 8. As a result, the program data at the address A1 in the instruction ROM 4 are modified into the program data at the address B1 on the modification target program storage memory A 8. In the same procedure, the program data at the address A2 is modified into the program data at the address B2.
6) The instruction acquisition unit 3 acquires instructions from the indirect call instruction row on the instruction ROM 4, and the execution unit 2 executes the instructions. If it is before the modification of the program (before the change of the indirect call table 10), the indirect call table 10 is referred to so as to acquire instructions from the address a1.
In reality, the indirect call table 10 is changed from the address a1 to the address b1, so that after the execution of the indirect call instruction, instructions are acquired from the address b1. This indicates that the program data at the address a1 in the instruction ROM 4 have been modified into the program data on the modification target program storage memory B 11.
In the above-mentioned procedure, inherently non-modifiable errors in the programs fixed on the instruction ROM or the like or found after the fabrication of ROM can be modified.
Of the modification target program storage memories A 8 and B 11 shown in FIG. 1, either one could be used, or they could be physically one.
As another conventional device, FIG. 3 shows another system which is basically the same the above-mentioned conventional device. In FIG. 3 a built-in ROM 41 corresponds to the instruction ROM 4 shown in FIG. 1, and a PC 1 and a decoder 2 correspond to the CPU core unit 1 shown in FIG. 1. The acquired instruction switch unit 6 is a kind of selector. When the program monitor unit 5 receives the address of a modification source program, the acquired instruction switch unit 6 receives the corresponding modification target program data from a modification target program memory 81 at the same time, and forwards the program data to the decoder 2.
These techniques will not be described any further because these are disclosed in Japanese Laid-Open Patent Applications No.7-73032, No.3-186927, No. 3-33926, U.S. Pat. No. 5,592,613, and the like.
(Background Art in Terms of the Problems the Invention is Going to Solve)
In the aforementioned structure, however, in order to modify a program at plural positions, a pair of modifying address registers are needed for each position. Therefore, as shown in FIG. 2 (2), a large number of registers are required as modifying address registers, which leads to an increases in hardware scale. (In storing the same amount of information, an increase in hardware scale is tremendous because registers demand about 50 times as large as circuit size as memories).
When program modification is performed by an indirect call, it is possible only from the position where the indirect call instruction row is arranged. Therefore, even when there are only a few steps in a program which are desired to be modified, it is necessary to store (or write), as a modified program, the steps from the indirect call instruction row portion to the modified portion which do not actually need to be modified. This unnecessarily increases the modification target program in size in the modification target program storage memories A 8 and B 11.
When the program modification device is incorporated into a system, programs are usually put in the form of ROM chips. When bugs are found in a ROMed program, the ROM must be modified; however, it takes about 5 weeks to complete modified ROM chips. This may cause to miss the timing of the introduction of a set device with the ROM chips on the market. Avoiding this program requires a ROM program modification function. However, the addition of the function leads to an increase in the number of registers (modifying address registers) which are highly unlikely used, thereby boosting the cost, or leads to the consumption of the memory to accommodate a large program to be modified (generally, flush memory in a microcomputer such as a system controller), which also boosts the cost.
In view of these problems, it has been desired to develop a program modification device which can use only a small number of modifying address registers and a minimum number of steps when a program contains lots of positions to be modified.
Besides the error correction of program data, it is often conducted to upgrade programs. In that case, it would become burdensome to users to purchase the whole device system where the whole new program is recorded. There are quite a few user requests for the upgraded or error-corrected portions only at a low price. Therefore, it would be advantageous for the manufactures in a field where upgrading occurs at high speed to design their devices to be capable of adding upgraded functions.
In order to address these needs, it has been desired to achieve a program modification device capable of addressing not only error correction but also upgrading easily and at a low cost, or a device which can have such a program modification device therein.
The present invention, which has been contrived in view of the above-mentioned problems, rewrites the contents of registers sequentially by the instructions and data contained in the modification target programs in memory (or in the programs in ROM before being modified). The details of the present invention are as follows.
In the invention of aspect 1, for each of the modification source program data not executed due to age or the presence of errors, modified modification target program data to be executed in place of the modification source program data are stored at predetermined addresses in memory for modification target program data which is usually composed of an inexpensive storage element or a storage medium. Moreover, the addresses of the modification source program data and the addresses of the corresponding modification target program data are recorded in pairs basically for each kind of error correction in a modifying address storage table made of an inexpensive storage element or the like.
Under these circumstances, the modifying address register writes programs for execution to the ROM so as to store the addresses of the program data for modification which are used to correct program errors found after the completion of ROM and the addresses of the modification source program data in pairs before the address unit executes the program data.
When modification instructions concerning (or received due to) the addresses for program modification stored in the modifying address register or load modification instructions are detected in a program in the process of being executed, the execution unit contained in the CPU core unit reads the addresses of the modification source program data and the addresses of the modification target program data from the modifying address storage table in accordance with the contents of the load modification instructions, and then loads (or stores) the addresses to the modifying address resister.
The program monitor unit refers to the modifying address resister either directly or indirectly and checks whether or not the address to be executed next (or a little bit earlier) in the program agrees with the address of the modification source program in the modifying address registers prior to the execution of the data at the address.
When the program monitor unit detects agreement between the addresses, the acquired instruction switch unit makes the address of the modification target program in the modifying address register the address of the program to be executed next by the CPU core unit. Thus, the error-containing modification source program data are replaced by modified program data.
Consequently, errors at any positions in a program can be corrected by the switch of an execution program having a minimum number of steps to be actually modified with the use of less hardware, which is a usually expensive modifying address register.
Unlike the invention of aspect 1, in the invention of aspect 2, the modifying address resister stores only the modification source addresses in order to minimize the register in size and other reasons. Detecting a load modifying instruction in a program, the execution unit contained in the CPU core unit stores only the addresses of the modification source program data to the modifying address register in accordance with the load modification instruction.
As a result, the acquired instruction switch unit finds the modification target address corresponding to the modification source address from the modification source address storage table, thereby making the modified program data corresponding to the address be executed.
Similar to the invention of aspect 2, in the invention of aspect 3, only modification source addresses are stored in the register. Moreover, there is some information to specify the modification target address on memory instead of this address. To be more specific, before or after the load modification instruction, the identifier of the load modification instruction is written on a specific memory so as to specify the modification target address from the identifier. In the invention of this aspect, the system needs only one such memory, which can downsize the memory.
Furthermore, the modification target program data are stored in memory in the order in which the programs are executed in such a manner that before and after the program data could be known. In that case, in the modifying address register, the addresses of the modification source program data are stored (or overwritten) in the order in which the programs are executed.
The invention of aspect 4 is characterized by comprising a modification target program storage memory which stores modification target programs, and in that the load modification instructions of the modifying address register are contained at the predetermined positions in a program in the modification target program storage memory. As a result, in accordance with the execution of a program in the CPU execution unit, the information on the address of the program data to be modified in the modifying address register is subjected to a modification process such as rewriting, prior to the execution of the program in the address unit. This can reduce the number of load modification instructions which are the load instructions to the modifying address register previously embedded in the instruction ROM.
The invention of aspect 5 is characterized in that a plurality of modifying address registers are correspondingly provided to the respective modification types, and that a plurality of load modification instructions to be loaded to the respective modifying address registers are contained in a program. As a result, in each modifying address register, program modification can be done independently in accordance with the type of modification determined by the contents of modification such as the modification of the program itself or the modification of data necessary for program execution.
The invention of aspect 6 is characterized in that the load modification instructions to be loaded from the modifying address storage table to the modifying address registers are included in the heads of task switch points and of interrupt-service routines.
Consequently, modification instructions are arranged at all the heads of the positions which operate asynchronously. Arranging and combining modification instructions in the modification target program storage memory in this manner makes it possible to embed the modification instructions only at the heads of the task switch points and of interrupt-service routines in the instruction ROM, thereby minimizing the number of modification instructions. When additional modification instructions are required, they can be arranged on the modification target program storage memory so as to realize program modification at a necessary number of positions.
The invention of aspect 7 is characterized in that the load modification instructions to be loaded from the modifying address storage table to the modifying address registers are contained at least in one of the heads of the task switch points, disk sync detection interrupt-service routines, error correction interrupt-service routines, host transfer interrupt-service routines, and servo-controlled routines. In the case of an optical disk controller, program modification can be realized by arranging a minimum number of modification instructions.
It goes without saying that in the invention of each aspect, the identifiers of the load modification instructions stored in the modification source registers, the modification target registers and the memories are saved before the occurrence of an interrupt service and then returned to their original states after the completion of the interrupt service.